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Field Effect Transistor Theory – Part 1


JFET symbols

As we continue to work through the Desulfator circuit we only have one device left that we have yet to talk about and that is the MOSFET.  A MOSFET is a type of Field Effect Transistor (FET).  Tonight we are going to point the ship toward understanding it, but to understand the operation of a MOSFET, we will talk first about a FET developed first called a JFET.  The J stands for Junction.   To understand this post it will be necessary to understand the PN Juncton of semiconductors.   My previous posts:  “The Chemistry of Semiconductors” and “Magic Crystals and Magic Potions … no just a real diode“ will be very helpful to understand this.

Conceptual N Channel JFET

Conceptual N Channel JFET

JFET’s come in two flavors, N Channel and P Channel.  Please refer to the diagram “Conceptual N Channel JFET”.    Inside the JFET the current flow of the majority carrier of the channel  material flowing from the Source to the Drain.   In the case of the N channel shown, electrons will flow from the Source to the Drain and that is the way I will talk about it throughout the rest of this discussion.   However, it is time deal with all the current types.    The IEEE standard currents are all going into the device so some would be negative values,   Technicians are normally taught with electron current flow going from negative to positive and conventional current flow is from positive to negative.   The point:  once you look outside the device, it will be necessary to talk about current flow in whatever system you are using.   Let’s just understand how it works and then in a 2nd step, convert to the current flow direction of the system of your choice.

The JFET is formed by doping the most of the silicon crystal with donor (N type) elements.   This makes the channel area of the JFET N type material.  On our conceptual diagram an area on either side of the channel is highly doped with acceptor elements and is p type material, but because it is highly doped we write p+.   The reason it is highly doped is to make it very conductive.   Some contact material, usually aluminium, is placed on the crystal as shown with the red blocks to provide connections to the outside world.   The two gate connections are wired together but are shown here as two separate connections just for clarity.   In following diagrams the connection on the right is dropped but it should be understood it is connected to the other gate connection.

Low Voltage on across the channel and low voltage on the gate.

Low Voltage on across the channel and low voltage on the gate for an N channel JFET.

To understand what is happening inside the N-channel JFET refer to the third picture.  We place a very small voltage across the channel by making the drain +0.1 V compared to the source.   This will cause an electron current to flow from the drain to the source.    Now, we also apply a negative voltage on the gate compared to the drain.  This voltage is called a bias voltage because as we will soon see it has an effect on the main channel current flow. The negative gate connection reverse biases the PN junction and the negative charge will cause the free electrons within the channel to be repelled from the gate area and will narrow the channel area.   The gate must always be negative or zero in relation to the channel for an N-channel JFET because we do not want forward bias the PN junction. If we did forward bias the PN junction, excessive currents would flow and destroy the device.

Pinch-off with Low Vds voltage.

Pinch-off with Low Vds voltage.

If we keep the very small voltage across the drain to source connection and increase the reverse bias on the gate we will continue to decrease the channel area.   Eventually we would decrease the area to the point where we have completely squeezed it down to the point where next to no current would flow.  The analogy is very similar to squeezing a rubber hose with water flowing through it.   The term for the point where the gate bias completely closes off channel flow is called Pinch-Off Voltage.  With the small voltage from drain to source, called Vds,  the JFET effectively becomes a voltage controlled resistor.

If you remember when we dealt with Bipolar Junction Transistors, current must flow in the input circuit, the base, to control the main current from the emitter to the collector and a transistor was effectively a current amplifier.   One of the really nice thing about FET’s is no (actually a very small amount) of current flowing in the input circuit.   This makes the input impedance of a JFET much much higher than the input impedance of a BJT circuit.   Way back there when I talked about the Input impedance of the actual op-amp we were experimenting with we had some problems using the amplifier with high resistor values.   If it was really necessary to work with those high resistance values, we could have looked for an op-amp with FET inputs and could probably have found an op-amp that would work with the higher value resistors.   The Digital Multi-Meter (DMM) I use has a FET input to obtain the high input impedance of 10 MΩ.

If we had been working with a p-channel JFET everything would have been exactly the same except the channel would have been doped with acceptor atoms (P-type), the gate material would have been highly doped with donor atoms (N+) and the two voltages would be of opposite polarity.   We would have talked about hole flow through the channel.  In my typical vernacular…. it is the same…only different.   Sorry, I can’t help myself.

We have more to cover about the JFET before we move on to a MOSFET.  In the next post we will increase the Vds voltage and see what happens as this voltage is increased.


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1 comment to Field Effect Transistor Theory – Part 1

  • […] In Part 1 we introduced a conceptual diagram of the construction of a JFET and talked about what happens if the gate voltages is changed in comparison to the source while the drain to source voltage is kept at a low value. Today we are going to start out talking about what happens if the gate voltage is kept at the same voltage as the source. Later we will create a graph to show both the gate and the drain voltage changing. […]

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